The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a hard disk drive (HDD) 10 includes a hard disk assembly (HDA) 12 and a HDD printed circuit board (PCB) 14. The HDA 12 includes one or more circular platters 16, which have magnetic surfaces that are used to store data magnetically. Data is stored in binary form as a magnetic field of either positive or negative polarity. The platters 16 are arranged in a stack, and the stack is rotated by a spindle motor 18. At least one read/write head (hereinafter, “head”) 20 reads data from and writes data on the magnetic surfaces of the platters 16.
Each head 20 includes a write element, such as an inductor, that generates a magnetic field and a read element, such as a magneto-resistive (MR) element, that senses the magnetic field on the platter 16. The head 20 is mounted at a distal end of an actuator arm 22. An actuator, such as a voice coil motor (VCM) 24, moves the actuator arm 22 relative to the platters 16.
The HDA 12 includes a preamplifier device 26 that amplifies signals received from and sent to the head 20. When writing data, the preamplifier device 26 generates a write current that flows through the write element of the head 20. The write current is switched to produce a positive or negative magnetic field on the magnetic surfaces of the platters 16. When reading data, the magnetic fields stored on the magnetic surfaces of the platters 16 induce low-level analog signals in the read element of the head 20. The preamplifier device 26 amplifies the low-level analog signals and outputs amplified analog signals to a read/write channel module 28.
The HDD PCB 14 includes the read/write channel module 28, a hard disk controller (HDC) module 30, a processor 32, a spindleNCM driver module 34, volatile memory 36, nonvolatile memory 38, and an input/output (I/O) interface 40. During write operations, the read/write channel module 28 may encode the data to increase reliability by using error-correcting codes (ECC) such as run length limited (RLL) code, Reed-Solomon code, etc. The read/write channel module 28 then transmits the encoded data to the preamplifier device 26. During read operations, the read/write channel module 28 receives analog signals from the preamplifier device 26. The read/write channel module 28 converts the analog signals into digital signals, which are decoded to recover the original data.
The HDC module 30 controls operation of the HDD 10. For example, the HDC module 30 generates commands that control the speed of the spindle motor 18 and the movement of the actuator arm 22. The spindle/VCM driver module 34 implements the commands and generates control signals that control the speed of the spindle motor 18 and the positioning of the actuator arm 22. Additionally, the HDC module 30 communicates with an external device (not shown), such as a host adapter within a host device, via the I/O interface 40. The HDC module 30 may receive data to be stored from the external device, and may transmit retrieved data to the external device. The HDC module 30 may use the volatile memory 36 to buffer data.
The processor 32 processes data, which includes encoding, decoding, filtering, and/or formatting the data. Additionally, the processor 32 processes servo or positioning information to position the heads 20 over the platters 16 during read/write operations. Servo, which is stored on the platters 16, ensures that data is written to and read from correct locations on the platters 16. In some implementations, a self-servo write (SSW) module 42 may write servo on the platters 16 using the heads 20 prior to storing data on the HDD 10. The nonvolatile memory 38 may store commands that the processor 32 uses to process the data.
The magneto-resistive read element in the head 20 typically comprises a sensing layer made of MR material. The resistance of the MR material in the sensing layer changes in response to changing magnetic field. The change in resistance enables the MR read element to detect magnetic flux transitions associated with bit patterns (i.e., 1s and 0s) recorded on the magnetic surfaces of the platters 16.
Typically, either current or voltage biasing is employed in the preamplifier device 26 to bias the MR read element for sensing and interpreting the changes in resistance of the MR read element. In current biasing, a predetermined biasing current (e.g., 0.1 to 3 mA) is typically passed through the MR read element to sense the changes in the resistance of the MR read element. Alternatively, in voltage biasing, a predetermined biasing voltage (e.g., 75 to 200 mV) may be applied across the MR read element.
As the MR read element senses the magnetic flux reversals when reading 1s and 0s in bit patterns, the preamplifier device 26 measures change in voltage across the MR read element. The change in voltage is the product of the change in resistance of the MR read element and the bias current passing through the MR read element. The preamplifier device 26 determines the change in the resistance of the MR read element from the change in voltage. Subsequently, the preamplifier device 26 generates a read signal having a voltage proportional to the change in resistance. The voltage of the read signal represents data read by the MR read element.
Accuracy of data read by a MR read element (hereinafter MR head) may be increased by calibrating a bias voltage that is used to bias the MR head. The MR head, however, may be damaged during calibration if the voltage applied to the MR head overshoots, that is, exceeds a maximum voltage that can be applied to the MR head. The maximum voltage that can be applied to the MR head is generally a design parameter assigned by a manufacturer based on the design of the MR head.
Referring now to FIG. 2, a system 100 for calibrating the bias voltage of the MR head is shown. The system 100 may be implemented in a preamplifier device of a disk drive (not shown). The system 100 comprises voltage regulators 102, 104, digital-to-analog converters (DACs) 106, 108, a MR head 110, a counter module 112, a reference generator 113, and a comparator 114.
The voltage regulators 102, 104 may be linear regulators that output a regulated voltage to the DACs 106, 108. The DACs 106, 108 source current that flows through the MR head 110. The amount of current that flows through the MR head 110 depends on an Icode count generated by the counter module 112. Current that flows through the MR head 110 generates a voltage drop Vmr across the MR head 110. Vmr is input to the comparator 114.
The reference generator 113 generates a reference voltage Vref, where Vref=Ipp*Rpp. Vref is approximately equal to a predetermined bias voltage Vbias specified by the manufacturer that may be applied to bias the MR head 110 during read operations. Vref is input to the comparator 114. The comparator 114 compares Vmr to Vref.
When Vmr<Vref, the counter module 112 increases the Icode count. Based on the increased value of Icode, the DACs 106, 108 increase the current that flows through the MR head 110. The increased current flowing through the MR head 110 increases Vmr. The comparator 114 compares the increased value of Vmr to Vref and indicates to the counter module 112 if Vmr≧Vref. The counter module 112 increases the Icode count until Vmr≧Vref.
Specifically, the counter module 112 increases the Icode count from 0000 to 0001, from 0001 to 0010, from 0010 to 0011, etc. until Vmr≧Vref. Incrementing the Icode count sequentially limits the maximum voltage by which Vmr may overshoot to a voltage increase generated by one LSB, which prevents the MR head 110 from being damaged during calibration.